The present invention relates to a method for reducing the settling time in PLL circuits.
More particularly, the invention relates to a method for reducing the settling time in PLL circuits used for example in digital cordless telephones (for example of the DECT type).
It is known that in recent years the world of wireless communications has changed very rapidly due, in part, to advances in silicon-based technologies, which have given great impulse to the use of electronic solutions of the monolithic type.
In particular, this technological impulse and market demand have led to the use of architectures of the RF transceiver which include the integration of the local oscillator, of the RF and IF transmitter and receiver section, and of part of the baseband circuits.
One of the blocks of an integrated transmitter is the PLL circuit.
In applications requiring a particularly short settling time, a frequency synthesizer is provided according to the block diagram shown in FIG. 1, in which the reference numeral 1 designates a clock signal which is input to a phase comparator 2, which is followed in a cascade configuration by a charge pump circuit 3 and by a filtering circuit 4. The voltage signal in output from the filtering circuit 4 is input to an adder 5, which receives, on its inverting input a signal that arrives from a DAC to which a digital word WORD is input.
The output of the adder 5 is sent to a voltage-controlled oscillator 6, which feeds back its output, by means of a divider 7, to the phase comparator 2.
The above-described block diagram differs from a conventional layout in that there is a digital-analog converter and an adder. The function of these elements is to perform the analog algebraic sum of the voltage VF that arrives from the filter 4 and of a reference voltage VDAC produced by the current IDAC on the feedback resistor RF of the adder circuit 5.
In formal terms, this is stated as follows:
VC=VFxe2x88x92RFIDAC(W)
where w is the digital word WORD input to the DAC 8.
The purpose of this structure is to provide, during channel transitions, by means of a suitable control of the DAC 8, a voltage RFIDAC which follows the variations of the control voltage, so as to leave the voltage across the filter 4 ideally constant.
In this manner, the settling time of the PLL circuit shown in FIG. 1 is limited only by the settling time of the voltage-controlled oscillator 6 and of the DAC 8 and is therefore very short.
In the real case, the voltage supplied by the DAC 8 is affected by a quantization error and accordingly, assuming that the channel transitions are instantaneous with respect to the reaction times of the PLL, this quantization error leads directly to an initial offset of the synthesized frequency (with respect to the steady-state value), according to a relation in which the frequency deviation is equal to the quantization error multiplied by the gain factor of the voltage-controlled oscillator 6.
If the locking conditions of the PLL are still met, this deviation is recovered by the synthesizer loop with a settling time which is directly proportional to said frequency deviation.
However, the efficiency of the system increases as the frequency deviation at the beginning of the transient decreases.
However, the need to cover the required synthesizing band regardless of process tolerances forces high values of the gain factor of the voltage-controlled oscillator 6.
This entails that in order to obtain a low settling time it is necessary to minimize the quantization error. This is achieved in conventional applications by using a DAC with a large number of bits.
This solution, however, entails several evident drawbacks. First of all, a large number of bits increases the complexity of the control logic of the system in which the PLL circuit is placed. Moreover, this solution also entails a higher consumption of current for an equal noise contribution and in most cases entails the use of complicated circuit topologies, with a consequent increase in silicon area occupation.
The present invention provides a method for reducing the settling time in PLL circuits in which it is possible to minimize frequency deviation in said circuits.
According to one aspect of the present invention, a method for reducing the settling time in PLL circuits that allows use of a DAC control logic that is proportionally simpler than known solutions is provided.
Another aspect of the present invention is to provide a method for reducing the settling time in PLL circuits to achieve reduced current consumption.
A further aspect of the present invention is to provide a method for reducing the settling time in PLL circuits to obtain less complicated DAC circuit topologies than known solutions and therefore with smaller silicon area occupations.
Yet another aspect of the present invention is to provide a method for reducing the settling time in PLL circuits that is highly reliable, relatively easy to provide, and at competitive costs.
These and other features and advantages, which will become apparent hereinafter, are achieved by a method for reducing the settling time in PLL circuits, particularly for use in an RF transceiver, that includes a phase comparator, a filter, a digital-analog converter, and an adder suitable to produce in output a voltage for controlling a voltage-controlled oscillator provided by means of a varactor. The method provides:
determining the dependency of the control voltage of the voltage-controlled oscillator on the frequency of a selected channel of a transmitter;
generating a law describing the variation of the output current of the digital-analog converter such that the voltage obtained from the output current of the digital-analog converter, added to an output voltage of the filter, is such as to keep the filter voltage constant, in order to reduce the settling time of the PLL circuit when changing a selected channel.